1. Field of the Invention
The present invention generally relates to a divider, and more particularly, to a divided-by-2N divider or a divided-by-(2N+1) divider.
2. Description of Related Art
Currently, as processing technologies advance, hand-held electronic products have become essential tools for human's daily life. In designing hand-held electronic products, reducing power consumption for extending lifetimes of batteries thereof, as well as lifetime of the hand-held electronic products are important issues. Referring to the equation of power consumption, i.e., P=αcv2f, wherein P is power consumption; α is an activity coefficient; v is a voltage value; and f is an operation frequency, it can be learnt that lowering operation voltage is the best way to reduce power consumption. However, in practical operation, lowering the operation frequency is often a must corresponding to the operation of lowering the operation voltage. Therefore, the concerns are turned to how to operate under a circumstance of a higher speed and a lower voltage.
For example, in a wireless communication system, a frequency synthesizer is often a very important basic unit, in which features of a press control oscillator and a divider including a pre-divider and a programmable counter circuit often determine performance of the frequency synthesizer in its entirety. FIG. 1A is a circuit diagram of a conventional divided-by-(⅔) divider. Conventional dividers are constituted of logic gates and D flip-flops. When a mode control signal MC is logic “0”, an output frequency OUT of the divider shown in FIG. 1A is equal to an input frequency CLOCK divided by 2. When the mode control signal MC is logic “1”, the output frequency OUT of the divider is equal to the input frequency CLOCK divided by 3. FIG. 1B is a circuit diagram of a conventional divided-by-(⅘) divider. When a mode control signal MC is logic “0”, an output frequency OUT of the divider shown in FIG. 1B is equal to an input frequency CLOCK divided by 4. When the mode control signal MC is logic “1”, the output frequency OUT of the divider is equal to the input frequency CLOCK divided by 5.